基于VHDL的自动打铃设计稿毕业设计稿.docVIP

基于VHDL的自动打铃设计 目录 摘要 (1) Abstract (2) 绪论 (3) 第1章 基本概念简介 (4) 1.1 VHDL简介 (4) 1.2 FPGA/CPLD简介 (4) 1.3 Quartus II的简介 (5) 第2章 设计整体概述 (6) 2.1 设计方案 (6) 2.2 设计原理图 (6) 2.3 设计流程图 (7) 第3章 各模块设计分析 (8) 3.1 计数器模块 (8) 3.1.1 秒和分计数器模块 (8) 3.1.2 时计数器模块 (10) 3.2 计时校时模块 (12) 3.3 打铃功能模块 (13) 3.4 顶层设计及原理图 (16) 第4章 引脚设定与下载验证 (19) 4.1 引脚设定 (19) 4.2 下载验证 (21) 总结 (22) 参考文献 (23) 致谢 (24) 附录 芯片引脚对照表 (25)  摘要 随着EDA 技术的发展和应用领域的扩大与深入，EDA 技术在电子信息、通信、自动控制及计算机应用领域的重要性日益突出。EDA 技术就是以计算机为工具，设计者在EDA软件平台上，对以硬件描述语言HDL（Hardware Description language)为系统逻辑描述手段完成的设计文件，然后由计算机自动地完成逻辑编译、化简、分割、综合、优化、布局、布线和仿真，直至对于特定目标芯片的适配编译、逻辑映射和编程下载等工作。 本设计是基于VHDL语言的自动打铃系统。在论文中，介绍了基于VHDL语言自动打铃系统的思路，整个系统需包含秒计时模块、分计时模块、时计时模块、校时模块、打铃模块。在Quartus II 开发环境中编译和仿真所设计的程序，并逐一调试验证程序的运行状况。仿真和验证的结果表明，该设计方法切实可行，该打铃系统可以实现调时定时打铃功能，具有一定的实际应用性。 关键字：EDA、VHDL、打铃、Quartus II Abstract With the development of EDA technology and the expansion of application, the function of EDA technology in the field of electronic information communication, automatic control and computer application, is becoming more and more important. EDA technology use computer as a tool. However, designers only need to use the hardware description language HDL to describe the system on the EDA software platform. Then computer automatically finishes partition, synthesis, optimization, simulation and other function until the electronic circuit system achieves the stated performance. This design is based on the VHDL hardware description language to project a system. I introduce ideas of the bell system in this design. All of the design includes second timer module, minute timer module, hour timer module, module to adjust time and module to ring the bell according to the require of design. I complete the description of different modules with VHDL language in the Quartus II development environment, and debug one by one to check the operational status of the verification process. Simulation results show that the design method is feasible, and the