FPGA论文：AVS视频解码芯片原型验证平台的研究和设计.docVIP

FPGA论文：AVS视频解码芯片原型验证平台的研究与设计 【中文摘要】随着高清数字时代的到来,视频编解码算法复杂度不断增加,视频编解码芯片规模越来越大,一款ASIC中往往集成了嵌入式处理器和大量的IP核,使得产品设计周期越来越长。验证所耗费的时间约占整个设计周期的70%到80%,因此成为VLSI设计的主要瓶颈。近几年来,FPGA在验证ASIC设计上的应用发展非常迅速,这是因为无论从规模上、物理结构上,还是从速度上,基于FPGA的原型与真实ASIC性能都非常接近,采用FPGA来模拟芯片设计的原型已被证明是最有效、最经济的方式。AVS视频解码芯片是一款集32位RISC处理器、视频解码模块、内存和片上总线为一体的SoC。针对国内外厂商推出的各类通用原型验证平台价格昂贵,结构冗余的问题,本文提出了一种适用于AVS视频解码芯片设计的原型验证平台。通过对AVS视频解码器逻辑资源和存储器的需求分析,选用了Altera公司单片高端大容量FPGA,克服了多片小容量FPGA带来的I/O紧张问题。平台采用子母板结构,按照AVS解码芯片功能进行了板级模块划分,提高了抗干扰能力,降低了设计成本。根据设计指标,能够满足AVS-P2标准下720p@60fps格式高清视频图像的解码要求。文章给出了平台硬件电路的设计和调试过程,并通过该平台搭建了基于OpenRISC1200 (OR1200)嵌入式处理器的SoC最小系统,利用Synopsys公司专门为高端FPGA原型设计打造的DC-FPGA工具进行逻辑综合,大大简化了OR1200 IP核从ASIC到FPGA的移植过程,从而实现了对AVS视频解码控制部分(OR1200处理器)的原型验证。本平台具有存储资源丰富,可重用性强和便于升级的特点,为AVS视频解码芯片设计的顺利进行铺平了道路。 【英文摘要】With high-definition digital era arriving, the complexity of video codec algorithm and the scale of video codec chip will increase more and more rapidly. Because of integration of embedded processor and many IP cores, ASIC design cycle will be much longer. In practice, time-consuming verification is common to spend 70-80% of the design cycle, thus become a major bottleneck of VLSI design. In recent years, FPGA application in ASIC verification increases quickly, because in terms of size, physical structure, and speed, the FPGA-based prototyping are very similar to ASIC. Using FPGA to emulate the ASIC has been proved to be the most effective and the most economical way.AVS video decoder is a SoC composed by 32-bit RISC processor, video decoding module, memory, and on-chip bus. Various common FPGA-based prototyping verification platforms have been launched by domestic company or foreign corporation, but they are expensive and structural superfluous, so the paper presents a kind of FPGA-based prototyping verification platform for video decoder chip design. With analysis for the logic resources and memory requirements of AVS video decoder, a single high-end high-capacity FPGA from Altera Corporation was selected to ov