VerilogHDL关于加法器优化的研究.pptVIP

Designing of Adder Lecturer：Prof. Wang Mingjiang Date: Theme：Algorithm of Adder 1.Full Adder 1.Full Adder Sum=A ^ B ^ Cin Cout=AB + BCin + ACin defination: carry delete: D=~A ~B carry propagate: P= A ^ B carry generate: G= A B 2. Ripple-carry Adder 2. Ripple-carry Adder 2. Ripple-carry Adder 2. Ripple-carry Adder 4. Mulitbit carry skip Adder 4. Mulitbit carry-skip Adder Carry-skip Adder VS Ripple carry adder 5. Carry-Select Adder 5. Carry-Select Adder 5. Carry-Select Adder 5. Carry-Select Adder 5. Carry-Select Adder Ripple carry adder VS Carry select adder 6. Carry-Look-ahead Adder 6. Carry-Look-ahead Adder 6. Carry-Look-ahead Adder 6. Carry-Look-ahead Adder 7. Binary Look-ahead Carry Adder 7. Binary Look-ahead Carry Adder 7. Binary Look-ahead Carry Adder 7. Binary Look-ahead Carry Adder Subtractor Subtractor Subtractor * * module fulladder( a,b,cin,sum,cout); input a, b, cin; output sum, cout; assign sum = a ^ b ^ cin; assign cout = ab | ac | bc ; endmodule module fulladder( a, b, cin, sum, cout ); input a, b, cin; output sum, cout; wire w1, w2, w3, w4; xor u1(w1, a, b); xor u2(sum, w1, cin); or u3(w2, a, b); and u4(w3, cin, w2); and u5(w4, a, b); or u6(cout, w3,w4); endmodule Carry-Chain of an RCA implemented using multiplexer from the standard cell library: module rca_4bits( a, b, cin, sum, cout); input [3:0] a, b; input cin; output [3:0] sum; output cout; fulladder u1( a[0], b[0], cin, sum[0], carry[0]); fulladder u2( a[1], b[1], carry[0], sum[1], carry[1]); fulladder u3( a[2], b[2], carry[1], sum[2], carry[2]); fulladder u4( a[3], b[3], carry[2], sum[3], cout); endmodule module rca_4bits( a, b, cin, sum, cout); input [3:0] a, b; input cin; output [3:0] sum; output cout; reg[3:0] sum, carry; integer I; always @( a, b, cin )