着名半导体公司 DFT_ATPG 内部培训资料 .pptVIP

DFT Signals DFT signals Ipt_mode_scan_xxx Ipt_se_xxx Ipt_se_async_xxx Ipt_se_gatedclkn/p_xxx Ipt_si/so_xxx Ipt_dbg_tck_xxx Ipt_dbg_trst_xxx Ipt_dbg_tms_xxx Ipt_dbf_tdi_xxx Ipt_dbg_tdo_xxx Please refer to Section 2.3 of WMSG - CD/MAD IP DFT Guidelines Agenda DFT Rules Combinational Loop Asynchronous Reset Tri-state Bus Contention Clock Dividers Clock Gating DFT signals For Scan For debug Soft IP tasks and deliverables Scripts and Demos QA What’s it? DFT Structured DFT ATPG Terminology in Scan Scan cell Scan chain Scan procedure Scan waveform Scan type Scan fault model Scan Coverage Soft IP Tasks Please refer to Section 2.1.1 of WMSG - CD/MAD IP DFT Guidelines Soft IP to SoC Deliverables Please refer to Section 2.1.2 of WMSG - CD/MAD IP DFT Guidelines Agenda DFT Rules Combinational Loop Asynchronous Reset Tri-state Bus Contention Clock Dividers Clock Gating DFT signals For Scan For debug Soft IP tasks and deliverables Scripts and Demos QA What’s it? DFT Structured DFT ATPG Terminology in Scan Scan cell Scan chain Scan procedure Scan waveform Scan type Scan fault model Scan Coverage Coverage Collection Demo 1. modify module.invoke file a. include the netlist you want to run fastscan b. change the top name 2. modify module_fs.dofile a. change Contrsints A, B, C, D for your module 3. modify module_fs.testproc a. change the alias for your module 4. modify chain_out.dofile a. add all the scan chains of your module 5. Command line: mkdir ./output ./module.invoke all the report and logfile will be put in the ./output QA * Design Verification, Testing and Diagnosis Design verification is to ascertain the design perform its specified behavior. It can be done by both simulation or formal verification. Testing of a system is an experiment in which system is exercised and its resulting response is analyzed to make certain of whether it behaved correctly. When incorrect behavior is detected, diagnosis is to locate