2012-2013-2《数字逻辑设计及应用》期末考试题.docVIP

电子科技大学2012 -2013学年第 二 学期期 末 考试 A 卷 课程名称：_数字逻辑设计及应用__ 考试形式： 闭卷 考试日期： 20 13 年 07 月 05 日 考试时长：_120___分钟 课程成绩构成：平时 30 %， 期中 30 %， 实验 0 %， 期末 40 % 本试卷试题由___七__部分构成，共__7___页。 题号 一 二 三 四 五 六 七 八 九 十 合计 得分 I. Fill out your answers in the blanks (3’ X 10=30’) 1. If a 74x138 binary decoder has 110 on its inputs CBA, the active LOW output Y5 should be ( ). 2. If the next state of the unused states are marked as “don’t-cares” when designing a finite state machine, this approach is called minimal ( ) approach. 3.The RCO_L of 4-bit counter 74x169 is ( ) when counting to 0000 in decreasing order. 4. To design a 001010 serial sequence generator by shift registers, the shift register should need ( ) bit at least. 5. One state transition equation is Q*=JQ’+K’Q. If we use T flip-flop with enable to complete the equation，the flip-flop should have the function EN=( ). 6. A 4-bit Binary counter can have ( ) normal states at most, 4-bit Johnson counter with no self-correction can have ( ) normal states, 4-bit linear feedback shift-register (LFSR) counter with self-correction can have ( ) normal states. 7. If we use a ROM, whose capacity is 16 × 4 bits, to construct a 4-bit binary code to gray code converter, when the address inputs are 1001, ( ) will be the output. 8. When the input isof an 8 bit DAC, the corresponding output voltage is 2V. The output voltage is ( ) V when the input is II. Please select the only one correct answer in the following questions.(2’ X 5=10’) 1. If a 74x85 magnitude comparator has ALTBIN=1, AGTBIN=0, AEQBIN=0, A3A2A1A0=1101, B3B2B1B0=0111 on its inputs, the outputs are ( ). A) ALTBOUT=0, AEQBOUT=0, AGTBOUT=0 B) ALTBOUT=1, AEQBOUT=0, AGTBOUT=0 C) ALTBOUT=1, AEQBOUT=0, AGTBOUT=1 D) ALTBOUT=0, AEQBOUT=0, AGTBOUT=1 2. As shown in Figure 1, what would the outputs of the 4-bit adder 74x283 be ( ) when A3A2A1A0=0100, B3B2B1B0=1110