003_语法【荐】.pptVIP

Chapter 4Modules and Ports 4.1 Modules A module definition always begins with the keyword module. The module name, port list, port declarations, and optional parameters must come first in a module definition. Port list and port declarations are present only if the module has any ports to interact with the external environment. The five components within a module are: variable declarations, dataflow statements, instantiation of lower modules, behavioral blocks, and tasks or functions. These components can be in any order and at any place in the module definition. The endmodule statement must always come last in a module definition. All components except module, module name, and endmodule are optional and can be mixed and matched as per design needs. Verilog allows multiple modules to be defined in a single file. The modules can be defined in any order in the file. a simple example of an SR latch // Module name and port list // SR_latch module module SR_latch(Q, Qbar, Sbar, Rbar); //Port declarations output Q, Qbar; input Sbar, Rbar; // Instantiate lower-level modules // In this case, instantiate Verilog primitive nand gates // Note, how the wires are connected in a cross-coupled fashion. nand n1(Q, Sbar, Qbar); nand n2(Qbar, Rbar, Q); // endmodule statement endmodule // Module name and port list // Stimulus module module Top; // Declarations of wire, reg, and other variables wire q, qbar; reg set, reset; // Instantiate lower-level modules // In this case, instantiate SR_latch // Feed inverted set and reset signals to the SR latch SR_latch m1(q, qbar, ~set, ~reset); // Behavioral block, initial initial begin $monitor($time, set = %b, reset= %b, q= %b\n,set,reset,q); set = 0; reset = 0; #5 reset = 1; #5 reset = 0; #5 set = 1; end // endmodule statement Endmodule In the SR latch definition above , notice that all components described in Figure 4-1 need not be present in a module. We do not find variable declarations, dataflow (assign) stateme