CPLD实现DDS信号源的设计_薛延侠.pdfVIP

2005 1 210 CPLD 实现DDS 信号源的设计 薛延侠, 赫建国 ( 710061) : 利用CPLD 在高速数据处理方面的特点设计出以VHDL 硬件描述语言为设计 入, 以 ALT ERA 公司的 EPM 7256 芯片为设计载体, 基于DDS 技术的任意波形信号发生器。该信号发生器能同时 出两路信号, 出信号的频率和两路 出信号之间的相位差可以步进调整。通过M ax+ Plus Ⅱ开发软件的时序分析表明, 该设计具有高精度的频率和相位调节能力, 相位调整的分辨率为12 位, 频率调整的分辨率为32 位。实测结果表明, 所讨论的方法和研制的系统是可行的、有效的。 : 复杂可编程逻辑; 直接数字频率合成; 信号产生器; 频率; 相位 : TN 11. 2: B: 1004 373X ( 2005) 1 073 03 Design of DDS Signal Generat or Based on CPLD , XUE Yanxia HE Jianguo ( , , 710061, ) Xi an Inst itute of Posts and T elecommunications Xi an China Abst ract :T his paper introduces the met hod of developing DDS signal generator by using t he VHDL hardware description lan- 7256 . guage as design input and the Altera s EPM chip as design carrier T wo signals with output frequency and phase difference ad- justable are generated.T he result of time analyzing show s that the signal generator has high accuracy on frequency and phase. It has achieved a phase resolution of 12 b and a frequency resolution of 32 b. The results of experiments have proved that the technique and system in t his paper are feasible and effective. : ; ; ; ; Keyw ords CPLD DDS signal generat or frequency phase ( CPLD) , ( EDA) CPLD 图1　DDS 技术产生任意波形原理图 1DDS DDS , , , , , , , ; , ( ,