数字电子技术pp7.ppt

7-1 Latches(锁存器) 7-2 Edge-Triggered Flip-Flops（边沿触发器） 7-3 Flip-Flop Operating Characteristic（触发器的操作特性） 7-4 Flip-Flop Application（触发器的应用） 7-5 One-shots（单稳态触发器） 7-6 The 555 Timer（555定时器） 7-1 Latches(a type of temporary storage device ） S-R (Set-Reset) latch（基本R-S触发器） Gated S-R latch（可控R-S触发器） 同步S－R触发器、主从J-K触发器（补充简介） Gated D latch（可控D触发器） S-R latch Figure 7–7 The 74LS279 quad latch. Gated S-R latch 同步触发器存在的问题：CP＝1的全部时间里，输入信号都会引起触发器输出状态的变化，降低了电路的抗干扰能力。 Latches Gated D latch（one input） The 74LS75 quad gated D latches. Figure 7–6 The latch used to eliminate switch contact bounce. 7-2 Edge-Triggered Flip-Flops （边沿触发的触发器） Edge-triggered S-R flip-flop Edge-triggered D flip-flop Edge-triggered J-K flip-flop Edge-triggered S-R flip-flop Figure 7–16 Edge-triggered D flip-flop Logic symbols for the 74AHC74 dual positive edge-triggered D flip-flop. Edge-triggered J-K flip-flop Asynchronous Preset and Clear inputs Logic symbols for the 74HC112 dual negative edge-triggered J-K flip-flop. 7-3 Flip-Flop Operating Characteristics （触发器的操作特性） Propagation delay times（传输延迟时间） Set-up time（建立时间） Hold time（保持时间） Maximum clock frequency（最大时钟频率） Pulse widths（脉冲宽度） Power dissipation（功率消耗） Figure 7–34 Set-up time (ts). The logic level must be present on the D input for a time equal to or greater than ts before the triggering edge of the clock pulse for reliable data entry. Figure 7–35 Hold time (th). The logic level must remain on the D input for a time equal to or greater than th after the triggering edge of the clock pulse for reliable data entry. 7-4 Flip-Flop Applications（触发器的应用） Parallel data storage（chapter 9） Frequency division Counting(chapter 8) others Frequency division The one-shot is a monostable(with only one stable state) device. It is normally in its stable state and will change to its unstable state only when triggered. Once it is triggered, the one-shot remains in its unstable state for a predetermined length of