SoftwareHardware CoDesign of Efficient and Secure Cryptographic Hardware.pdfVIP

Journal of Universal Computer Science, vol. 11, no. 1 (2005), 66-82 submitted: 15/7/04, accepted: 6/12/04, appeared: 28/1/05 © J.UCS Software/Hardware Co-Design of Efficient and Secure Cryptographic Hardware Nadia Nedjah (Department of Electronics Engineering and Telecommunications, Faculty of Engineering, State University of Rio de Janeiro, Rio de Janeiro, Brazil nadia@eng.uerj.br http://www.detel.eng.uerj.br) Luiza de Macedo Mourelle (Department of System Engineering and Computation, Faculty of Engineering, State University of Rio de Janeiro, Rio de Janeiro, Brazil ldmm@eng.uerj.br http://www.desc.eng.uerj.br) Abstract: Most cryptographic systems are based on the modular exponentiation to perform the non-linear scrambling operation of data. It is performed using successive modular multiplications, which are time consuming for large operands. Accelerating cryptography needs optimising the time consumed by a single modular multiplication and/or reducing the total number of modular multiplications performed. Using a genetic algorithm, we first yield the minimal sequence of powers, generally called addition chain, that need to be computed to finally obtain the modular exponentiation result. Then, we exploit the co-design methodology to engineer a cryptographic device that accelerates the encryption/decryption throughput without requiring considerable har