LDPC码研究译码器的FPGA设计.pdfVIP

摘要 低密度奇偶校验码（LDPC 码）是继Turbo 码后信道编译码领域又一重要进 展，自从上世纪60 年代提出和90 年代被重新发现，其以接近Shannon 限的优异 性能和较低的译码复杂度一直受到编码研究者的热衷。目前，LDPC 码已被 DVB-S2、WiMax 系统等做为编码标准，也已被4G 通信作为重点关注的纠错编 码方案，应用前景甚为广阔。 本文以LDPC 码译码算法为重点，在分析两类经典译码算法的基础上，提出 了一种改进的基于循环检测的硬判决译码算法，并结合硬件FPGA 设计了NMS 算法的译码器。 本文所作详细工作如下： 第一：在讨论了 LDPC 码基本概念原理同时，对 LDPC 码编码方案及其复 杂度分析，并就LDPC 码构造方案进行了比较，仿真分析（非）规则码的性能以 及校验矩阵H 中四环对码性能的影响。 第二：就译码纠错性能和复杂度两个方面，重点研究了LDPC 码两类译码算 法，对硬判决算法（BF 算法，WBF 算法，MWBF 算法，RRWBF 算法）和以 BP 算法为基础改进的几种软判决译码算法（对数域BP 算法，MS 算法及归一化 最小和NMS 算法和OMS 算法）进行详细分析比较，并在此基础上提出一种基 于“循环检测”的NBF/LD 硬判决算法，并对此算法和其它硬判决译码算法比较， 仿真表明该算法在运算复杂度不是很高的情况下译码性能改善明显。 第三：基于FPGA 译码器的设计，综合考虑逻辑资源与时钟频率，选择采用 部分并行译码方式，设计了NMS 算法的译码器。分析影响NMS 算法的各种参 数，给出了译码器各结构模块实现方案，运用Verilog 语言编写各模块，最终通 过Quartus II 开发平台进行功能时序仿真验证，满足了设计要求。 关键词：LDPC 码，循环检测，软/硬判决，部分并行译码，FPGA I Abstract Low-density parity-check codes (LDPC codes) is another important area of the channel encoding and decoding after Turbo codes. Since it was proposed in 1960s and was rediscovered in 1990s, it has become a hot spot and has been researchers’ sensation due to its excellent decoding performance and lower complexity. Currently, LDPC codes have been applied in DVB-S2 systems as coding standards. At the same time, it has become a focus encoding scheme in the 4G communications and its application prospect grew quite broadly. Based on the two classical decoding algorithms, this paper proposed an improved new algorithm based on loop detection, and designed a NMS algorithm decoder by combining with the FPGA. The detailed work was as follows: At first, this paper analyzed the principles of LDPC codes, and discussed two construction methods of LDPC codes based on its encoding complexity. By comparing