lattice_cpld概述.ppt

* * * * * ispATE Users Lattice’s ispATE Provides an Efficient Means of Developing Tester-specific Programming Vectors Several High-Volume PLD Users Have Implemented ispATE With Unparalleled Success. * * * * On this chart I am plotting performance as measured by fMAX versus density for 3.3-volt power supply devices. Here is the line for lattice. When you compare it against the sluggish performance of the Xilinx 9500XL and Altera Max 7000AE our leadership position is obvious. * On this chart I am plotting performance as measured by fMAX versus density for the fastest part at any power supply voltage. Here is the line for lattice. When you compare it against the sluggish performance of the Xilinx CoolRunner II and Altera Max 7000B our leadership position is obvious. * This graphic looks at density leadership. We are the clear density leaders with twice the density of Altera or Xilinx. * On this slide I plot power consumption for 64 macrocell devices filled with 16-bit counters and running at 100MHz. Here is the data for the Lattice 4000 devices at 3.3, 2.5, and 1.8-volts. Here is the data for the Altera and Xilinx products. As you can see we demonstrate leadership at 3.3 and 2.5-volts. * When presenting, skip the explanation for pins * The ISP Revolution Lattice ISP Provides Benefits Throughout the Product Lifecycle Design: Quick Design Changes Provide Improved Time-to-Market System Integration: Lattice ISP Devices Are Available In Space-Efficient TQFP And BGA Packaging. Eliminates the Need to Remove Devices From the Board to Perform Programming And Allows More Compact, Integrated Design Standards Manufacturing: Fast Programming Times, Turbo Programming, and Support for ATE Provides Significantly Reduced Manufacturing Costs Field Upgrades: Users Are Able to Remotely Upgrade Devices Extending Product Lifetimes and Reducing Maintenance Costs * Likewise this chart looks at logic width where we are the clear leaders with our 5000 family of CPLDs. *