ch可综合的Verilog设计课件.ppt

状态机设计（续） 2 状态跳转 // transition always @(posedege clk or negedge rst_n) begin if(!rst_n) current_state = SLEEP; else current_state = next_state; end 敏感信号表时钟信号以及复位信号边沿的组合 使用非阻塞赋值 状态机设计（续） 3 当前状态下的动作 // action wire read_book; assign read_book = (curretn_state ==STUDY) ? 1’b1: 1’b0; ... ... 4 下状态判断 // next state decision always @(current_state or input_signals) begin case (current_state) SLEEP: begin if(clock_alarm) next_state = STUDY; else next_state = S