MicrosemiIGL002FPGA系列开发方案.docx

Microsemi公司的IGL002 FPGA系列在单片上集成了第四代基于闪存的FPGA架构和高性能通信接口如PCI EXPRESS? (PCIe?), XAUI/XGMII以及SERDES和DDR2/DDR3存储器控制器,主要用在马达控制,系统管理,工业自动化和高速串行I/O应用如PCIe, SGMII和用户定制的串口.本文介绍了IGL002高性能FPGA主要特性,框图,以及IGLOO2开发板M2GL-EVAL-KIT硬件特性,框图,电路图,材料清单和PCB元件布局图.Microsemi’s IGLOO?2 FPGAs integrate fourth generation flash-based FPGA fabric and high-performance communications interfaces on a single chip. The IGLOO2 family is the industry’s lowest power, most reliable and highest security programmable logic solution. This next generation IGLOO2 architecture offers up to 3.6X gate count implemented with 4-input look-up table (LUT) fabric with carry chains, giving 2X performance, and includes multiple embedded memory options and mathblocks for digital signal processing (DSP). High speed serial interfaces include PCI EXPRESS? (PCIe?), 10 Gbps attachment unit interface (XAUI) / XGMII extended sublayer (XGXS) plus native serialization/deserialization (SERDES) communication, while double data rate 2 (DDR2)/DDR3 memory controllers provide high speed memory interfaces.IGL002高性能FPGA主要特性:IGLOO2 Family High-Performance FPGA? Efficient 4-Input LUTs with Carry Chains for High-Performance and Low Power? Up to 236 Blocks of Dual-Port 18 Kbit SRAM (Large SRAM) with 400 MHz Synchronous Performance (512 x 36, 512 x 32, 1 kbit x 18, 1 kbit x 16, 2 kbit x 9, 2 kbit x 8, 4 kbit x 4, 8 kbit x 2, or 16 kbit x 1)? Up to 240 Blocks of Three-Port 1 Kbit SRAM with 2 Read Ports and 1 Write Port (micro SRAM)? High-Performance DSP Signal Processing– Up to 240 Fast Mathblocks with 18 x 18 Signed Multiplication, 17 x 17 Unsigned Multiplication and 44-Bit AccumulatorHigh Speed Serial Interfaces? Up to 16 SERDES Lanes, Each Supporting:– XGXS/XAUI Extension (To Implement a 10 Gbps (XGMII) Ethernet PHY Interface)– Native SERDES Interface Facilitates Implementation of Serial RapidIO in Fabric or an SGMII Interface to a soft Ethernet MAC– PCI Express (PCIe) Endpoint Controller x1, x2, x4 Lane PCI Express CoreUp to