简易计算器 2.docVIP

青海师范大学毕业论文 论文题目：基于EDA的简易计算器的设计 系　　别：物理系 专　　业：电子信息工程 班　　级：09 C 学生姓名：陈雪丽 学号：20091711335 指导教师姓名：赵建飞 职称：讲师 最后完成时间： 2013 年 5 月 10 日  PAGE \* MERGEFORMAT IV 基于EDA的简易计算器的设计 中文摘要 EDA是指利用计算机完成电子系统的设计。在基于EDA的计算器的设计中，主要研究了的是8位二进制数的加减法运算、两个4位二进制数的乘法运算、8位二进制数除以4位二进制数的除法运算以及连续的加减运算的实现方法。本系统选用Altera公司的MAX+PluseⅡ作为硬件开发平台,并采用VHDL语言进行电路设计。在设计的过程中采用的是分模块的设计方法，将计算器分为四个部分：计算部分、存储部分、显示部分和输入部分。计算部分主要有加法器、减法器、乘法器和除法器组成。存储部分需要3个存储器来实现：内部累加器（acc）、输入寄存器以及结果暂存器。显示部分由三个7段译码器组成，分别来显示输入数字。输入部分是由0——9十个数字按键、加减乘除四则运算的运算符按键、一个等号按键和一个清零按键组成的，设计所要做的是对按键信息进行译码（将十进制数转换成为二进制数），使其在计算机内部可以使用。 关键词：可编程逻辑器件，加法器，乘法器 ，计算器 ，系统仿真 软件设计 Abstract EDA is the used of the computer to complete the design of electronic systems. The calculator based on EDA design, it main studies the 8-bit binary number of addition and subtraction operations, the two 4-bit binary number multiplication, 8-bit binary number divided by the number of four binary division, as well as implementation for continuous operation of addition and subtraction operations. The system selected Alteras MAX + Pluse Ⅱ as a hardware development platform, and the use of VHDL design languages. In the design process is used frequency division modules, the calculator is divided into four parts: calculate, storage, display and input part. The calculate is composed of four parts：addertion, subtraction, and multiplier and divider components. Storage part needs three memory to help achieved: internal accumulator (acc), input register (reg) as well as the results of registers (ans). Display part is made up three decoder of 7 sections, respectively to show the number of input. Input part has ten number keys, from 0 – 9, also has addition and subtraction and multiplication and division arithmetic operator keys, a button and of equal sign and the clear key, the design has to decode the key information (to be decimal digital conversion as a binary number), so that you can use these in the internal of calculator. Key