格雷码和二进制的相互转换-vhdl程序.docxVIP

B2G_converter Screenshot of iSim simulation results: note: from the beginning point at 1,000ns, input(i5binary) changes every other 50ns i5binary input from 0 to 6 i5binaryo5graycodeDelay of output (ns)00000000006.69100001000016.51600010000116.51700011000106.51600100001106.58000101001116.51600110001016.517 i5binary input from 7 to 13 i5binaryo5graycodeDelay of output (ns)00111001006.51601000011006.19701001011016.51601010011116.51701011011106.51601100010106.58001101010116.516 i5binary input from 14 to 20 i5binaryo5graycodeDelay of output (ns)01110010016.51701111010006.51610000110005.21010001110016.51610010110116.51710011110106.51610100111106.580 i5binary input from 21 to 27 i5binaryo5graycodeDelay of output (ns)10101111116.51610110111016.51710111111006.51611000101006.19711001101016.51611010101116.51711011101106.516 i5binary input from 28 to 31 i5binaryo5graycodeDelay of output (ns)11100100106.58011101100116.51611110100016.51711111100006.516 VHDL for Binary-to-Gray-Code converter: ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:02:37 09/15/2015 -- Design Name: -- Module Name: b2g_converter - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity b2g_converter is Port ( i5Binary : in ST