lecture0.pptVIP

Advanced Digital Design with the Verilog HDL (Lecture0) HIT Shenzhen Graduate School Sep.1, 2007 Course Overview Objective: emphasis of the course is on using Hardware Description Languages (HDLs) for the design and synthesis of digital systems. Includes a comprehensive presentation of the Verilog HDL. Provides an overview of related digital system design concepts and topics (VHDL, SystemC, language synthesis, HDL tools,programmable logic tools). Course Overview Office hours: Wednesday 18:30-21:30 Office: A405 Course Background Digital Design – logic, finite state machines, etc Computer Organization –pipelining Programming Languages – Syntax, compilation Course Overview Tools: ModelSim and NC-Verilog, VCS – Windows/Linux – Free Course Administration ? Grading – Project – Final Exam Modeling Digital Systems HDL is for writing models of a system – Growing complexity of designs ? Reasons for modeling – Requirements specification – Documentation – Testing using simulation – Formal verification – Synthesis ? Goal – Most reliable design process, with minimum cost and time – Avoid design errors before fabrication Modeling Digital Systems Originally, HDLs were used to simulate the functionality of circuit (high-level) – HDL started to become the specification – Defines the design, instead of being between design process and implementation step ? Originally, HDLs were used to test and exercise a design – Logic synthesis tools became available to automatically translate the HDL into an implementation – Varying degrees of success – Full-custom VLSI, ASICs, FPGAs HDL Issues Many people think that design is a straight-forward logical process – Start with the idea of what you need to build – And then you build it ? Real design is not like that – Goal might be straightforward, but ... – Path to the goal has a number of decision points – Changes cause a ripple effect ? Unclear or incomplete specification ? Imp