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The Design of a Radiation Tolerant, Low Power, High Speed Phase.ppt

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The Design of a Radiation Tolerant, Low Power, High Speed Phase

Tiankuan Liu,TWEPP09 Paris France Sep 2009 The Design of a Low-Power High-Speed Phase Locked Loop Tiankuan Liu1, Datao Gong1, Suen Hou2, Zhihua Liang1, Chonghan Liu1, Da-Shung Su2, Ping-Kun Teng2, Annie C. Xiang1, Jingbo Ye1 1 Department of Physics, Southern Methodist University, Dallas TX 75275, U.S.A. 2 Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwan liu@mail.physics.smu.edu Outline Introduction PLL Design Block diagram Layout VCO design and simulation Divider design and simulation PLL performances Acquisition time Deterministic jitter Random jitter Conclusion Acknowledgments Introduction Silicon-on-Sapphire SoS CMOS technology High speed, low power, high quality inductors, no latch-up The radiation tolerance of a commercial 0.25 μm SoS CMOS technology has been evaluated in the previous study Design Goals: Operation frequency: 4 ~ 5 GHz for data rate 8 ~ 10 Gbps Random jitter 1 ps RMS Power consumption 100 mW PLL Design: Block Diagram PLL Design: Shared Blocks The LVDS receiver, the phase frequency detector PFD , the charge pump, the pass filter, the CMOS divider, and the CML driver are shared with the 5 Gbps 16:1 serializer. For details of these design blocks please see the poster “A 16:1 serializer for data transmission at 5 Gbps” presented by Dr. Datao Gong at TWEPP, Paris France, September, 2009. The bandwidth of the low pass filter and the current of charge pump are programmable to suit different applications. The loop bandwidth and the phase margin are calculated in the following table. PLL Design: Layout Area 1.4 mm x 1.7 mm PLL Design: VCO PLL Design: VCO Schematic PLL Design: VCO Simulation The tuning range is 3.79 – 5.01 GHz at the typical corner and room temperature and varies less than 8% in all corners and temperature range. PLL Design: Dividers The divider consists of a CML divider divide by 2 , a CML to CMOS converter, and a CMOS divider divide by 8 The dividers can work up to 5.1 GHz at all corners from -