EDA与VHD上例题.docVIP

1、（1）2选1多路选择器的VHDL描述： ENTITY mux21a IS PORT( a, b : IN BIT ; s : IN BIT; y : OUT BIT ) ; END ENTITY mux21a ; ARCHITECTURE one OF mux21a IS BEGIN y = a WHEN s = 0 ELSE b ; END ARCHITECTURE one （2）2选1多路选择器的VHDL描述（并行语句用布尔方程式表达） ENTITY mux21a IS PORT ( a, b : IN BIT; s : IN BIT; y : OUT BIT ); END ENTITY mux21a; ARCHITECTURE one OF mux21a IS SIGNAL d,e : BIT; BEGIN d = a AND (NOT S); e = b AND s; y = d OR e; END ARCHITECTURE one; （3）2选1多路选择器的VHDL描（用顺序语句） ENTITY mux21a IS PORT ( a, b, s: IN BIT; y : OUT BIT ); END ENTITY mux