[1920现代CMOS工艺基本流程英文.ppt

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[1920现代CMOS工艺基本流程英文

* Source/Drain Formation Deposit Silicon Nitride Layer: Using Chemical Vapor Deposition, thickness 1200-1800?. Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well Silicon Nitride Thinner Here Thicker Here N Tip P Tip Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. * Source/Drain Formation Etch Nitride to Form Spacer Sidewalls: Using a carefully controlled RIE etch, the thin nitride is removed from the horizontal surfaces, but the sidewalls remain. These sidewalls will precisely position the implants that form the transistor sources and drains. Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well Spacer Sidewall N Tip P Tip Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. * Source/Drain Formation Pattern Photoresist for NMOS Transistor Source/Drain Implant: Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well Photoresist N Tip P Tip Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. * Source/Drain Formation NMOS Transistor Source/Drain Implant: A shallow and high-dose implant of arsenic ions completes the formation of the heavily-doped NMOS transistor source and drain. The spacer shadows the implant near the gate region. Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well Photoresist Arsenic (-) Ions N+ Source N+ Drain P Tip Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. * Source/Drain Formation Strip Photoresist: Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Source N+ Drain P Tip Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. * Source/Drain Formation Pattern Photoresist for PMOS Transistor Source/Drain Implant: Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Sour

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