第3讲器件讲义.pptVIP

Sub-Threshold ID vs VGS VDS from 0 to 0.5V Sub-Threshold ID vs VDS VGS from 0 to 0.3V MOS管亚阈值导电特性的Pspice仿真结果 VgS logID 仿真条件： VT＝0.6Ｖ W/L＝100μ/2μ MOS管亚阈值电流ID一般为几十~几百nA, 常用于低功耗放大器、带隙基准设计。 Summary of MOSFET Operating Regions Strong Inversion VGS VT Linear (Resistive) VDS VDSAT Saturated (Constant Current) VDS ? VDSAT Weak Inversion (Sub-Threshold) VGS ? VT Exponential in VGS with linear VDS dependence Latch-up MOS器件版图 MOS CapacitancesDynamic Behavior MOS结构电容 t ox n + n + Cross section L Gate oxide x d x d L d Polysilicon gate Top view Gate-bulk overlap Source n + Drain n + W MOS器件寄生电容 栅源、栅漏电容随VGS的变化曲线 C3=C4=COVW Cov：每单位宽度的交叠电容 MOS管关断时: CGD=CGS=CovW, CGB=C1//C2 C1=WLCox MOS管深线性区时: CGD=CGS=C1/2+CovW, CGB=0, C2被沟道屏蔽 MOS管饱和时: CGS= 2C1/3+CovW ,CGD=CovW, CGB=0, C2被沟道屏蔽 沟道电容 Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off 沟道电容 Capacitance as a function of VGS (with VDS = 0) Capacitance as a function of the degree of saturation 电路模拟器提取电容 Diffusion Capacitance 结电容 Bottom Side wall Side wall Channel Source N D Channel-stop implant N A 1 Substrate N A W x j L S Junction Capacitance 减小MOS器件电容的版图结构 对于图a:CDB=CSB = WECj + 2(W+E)Cjsw 对于图b: CDB=(W/2)ECj+2((W/2)+E)Cjsw CSB=2((W/2)ECj+2((W/2)+E)Cjsw = WECj +2(W+2E)Cjsw Dynamic Behavior of MOS Transistor 寄生电容 CGS=CGCS+CGSO; CGD=CGCD+CGDO; CGB=CGCB; CSB=CSdiff; CDB=CDdiff; Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest Capacitances in 0.25 mm CMOS process 源－漏电阻 栅极电阻 完整的MOS小信号模型 NMOS器件的电容--电压特性 积累区 强反型 Future Perspectives 25 nm FINFET MOS transistor EE141 * * 假定漏极电压0，由于沟道电势从源极的0V变化到漏极的VD，所以栅与沟道间的局部电压差从VG变化到VG-VD。 NMOS管VGSVT、VDSVGS-VT时的示意图 电子 耗尽区 NMOS管的电流公式 截至区，VgsVTH 线性区,Vgs VTH VDS Vgs - VTH 饱和区,Vgs VTH VDS Vgs - VTH MOSFET的I/V特性 Triode Region VDSVGS-VT 沟道电阻随VDS增加而增加导致曲线弯曲 曲线开始斜率正比于VGS-VT