第5章设计实例报告.ppt

process(cnt1) begin if cnt1=9 then cntout=1; else cntout=0; end if; end process; cntQ=cnt1; end a; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity freq_t is port(clk:in std_logic; freq_en:out std_logic; cnt_clr:out std_logic; load: out std_logic ); end freq_t; architecture a of freq_t is signal div2clk:std_logic; begin process(clk) begin if clkevent and clk=1 then div2clk=not div2clk;-------------2分频 end if; end process; process(clk,div2clk) begin if clk=‘0’and div2clk=‘0’ then—产生计数器清零信号 cnt_clr=1; else cnt_clr=0; end if; end process; load= not div2clk; freq_en=div2clk; end a; library IEEE; use IEEE.std_logic_1164.all; entity dlatch24 is port(load:in std_logic; din:in std_logic_vector(23 downto 0); dout:out std_logic_vector(23 downto 0) ); end dlatch24; architecture a of dlatch24 is begin process(load,din) begin if loadevent and load=1 then dout=din; end if; end process; end a; library IEEE; use IEEE.std_logic_1164.all; entity freq24t is port(clk:in std_logic; freqin:in std_logic; result_out:out std_logic_vector(23 downto 0) ); end freq24t; architecture a of freq24t is component freq_t port(clk: in std_logic; freq_en:out std_logic; cnt_clr:out std_logic; load: out std_logic); end component; component count10 port(clk:in std_logic; clr:in std_logic; ena:in std_logic; cntq:out std_logic_vector(3 downto 0); cntout:out std_logic ); end component; component dlatch24 port(load:in std_logic; din:in std_logic_vector(23 downto 0); dout:out std_logic_vector(23 downto 0) ); end component; signal freq_en1:std_logic; signal cnt_clr1:std_logic; signal load1:std_logic; signal dlatch1:std_logic_vector(23 downto 0); signal cntout1:std_logic_vector(23 downto 0); begin u1: freq_t port map(clk=clk,