时序电路计数器的设计报告.docxVIP

实验二、时序电路——计数器的设计一、实验目的了解EDA实验箱分别用电路图和VHDL语言设计计数器的原理，设计相应得计数器模块，以备后面实验用。二、硬件要求主芯片为Cyclone V E，型号为EP4CE22F17C8，时钟信号，拨码开关。三、实验源程序：（1）用VHDL实现模16 加法计数器(cnt16.vhd)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt16 is port(clk,rst,en : in std_logic; cq : out std_logic_vector(3 downto 0); cout : out std_logic );end cnt16;architecture behave of cnt16 isbegin process(clk,rst,en) variable ci:std_logic_vector(3 downto 0); begin if rst=1 then ci:=(others=0);--计数器异步复位 elsif clkevent and clk=1 then if en=1 then --检测是否允许计数 if ci1111 then ci:=ci+1; --允许计数， else ci:=(others=0); --等于15，计数值清零 end if; end if; cq=ci; end if; if ci=1111 then cout=1; --输出进位信号 else cout=0; end if; end process;end behave; (2) 计数器的级连：分别用VHDL语言实现模10和模6计数器，然后通过顶层电路调用模10和模6计数器，产生模60进制计数器。10进制计数器源程序：cnt10.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity cnt10 isport(clk,rst,en: in std_logic; sum: out integer range 15 downto 0; cout1: out std_logic); end cnt10;architecture a of cnt10 issignal count: integer range 15 downto 0;beginprocess(clk,rst)begin if rst=0 then count=0; elsif rising_edge(clk) then if en=1 then if count=9 then count=0; else count=count+1; end if ; end if; end if;end process;sum=count;cout1=1 when en=1 and count=0 else 0;end a;6进制计数器源程序:：cnt6.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity cnt6 isport(clk,rst,en: in std_logic; sum: out integer range 7 downto 0; cout2: out std_logic); end cnt6;architecture a of cnt6 issignal count: integer range 7 downto 0;beginprocess(clk,rst)begin if rst=0 then count=0; elsif rising_edge(clk) then if en=1 then if count=5 then count=0; else count=count+1; end if ; end if; end if;end process;sum=count;cout2=1 when en=1 and count=0 else 0;end a;60进制计数器原理图：cnt60.gdf把10进制计数器的进位信号与6进制计数器的时钟信号相连接七、波形仿真结果