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Tables and Charts Extra Slides Quick Loops Hydra Speculation Hardware Modified Bit Pre-invalidate Bit Read Bits Write Bits The goal of any high-performance architecture is to exploit program parallelism. Now parallelism exists at multiple levels. At the lowest level is the parallelism between instructions in a basic-block, Above that is the loop-level parallelism between loop iterations. Above this is thread-level parallelism that comes from parallelizing a single application either manually or automatically. At the highest level is the parallelism between separate processes in a multiprogramming environment. The granularity of parallelism typically increases as the level of parallelism increases. Superscalar architectures concentrate on exploiting ILP and to some extent LLP, but these techniques are complex and do not scale well in advanced semiconductor technologies. So this begs the question * The approach we have taken in Hydra is multiprocessor built out of simple processors that can be designed for high speed. The main advantage that this architecture is multiple threads of control which enables parallelism to be exploited that is much more widely distributed in the program than is possible with a single hardware window. Secondly, if each of the processors is tightly integrated with its first level cache the highest speed paths can be localized to reduce the impact of wire delay and make it possible to achieve very high clock frequencies. The disadvantage of this architecture is that it requires parallel programs to run on more than one processor. We use thread level speculation to simplify the process of creating parallel programs. Our overall design approach in Hydra is to keep the basic MP architecture as simple as possible by taking advantage of the fact that we are on single piece of silicon. We’ll see how we do this. * The problem is that the amount parallel software is limited. Today, most parallel software is generated manually. This
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