Design Automation for Streaming Systems流媒体系统的设计自动化.pptVIP

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Design Automation for Streaming Systems流媒体系统的设计自动化.ppt

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12/2/05 Eylon Caspi Design Automationfor Streaming Systems Eylon Caspi University of California, Berkeley 12/2/05 Outline Streaming for Hardware From Programming Model to Hardware Model Synthesis Methodology for FPGA Streams, Queues, SFSM Logic Characterization of 7 Multimedia Apps Optimizations Pipelining, Placement, Queue Sizing, Decomposition Large System Design Challenges Devices growing with Moore’s Law AMD Opteron dual core CPU: ~230M transistors Xilinx Virtex 4 / Altera Stratix-II FPGAs: ~200K LUTs Problems of DSM, large systems Growing interconnect delay, timing closure “Routing delays typically account for 45% to 65% of the total path delays” (Xilinx Constraints Guide) Slow place-and-route Design complexity Designs do not scale well on next gen. device; must redesign Same problems in FPGAs Limitations of RTL RTL = Register Transfer Level Fully exposed timing behavior always @(posedge clk) ... Laborious, error prone Unpredictable interconnect delay How deep to pipeline? Redesign on next-gen device Undermines reuse Existing solutions Modular design ? Floorplanning Physical synthesis ? Hierarchical CAD Latency insensitive communication Streams A better communication abstraction Streams connect modules FIFO buffered channel (queue) Blocking read Timing independent (deterministic) Robust to communication delay Pipeline across long distances Robust to unknown delay Post-placement pipelining Alternate transport (packet switched NOC) Flexibly timed module interfaces Robust to module optimization (pipeline, reschedule, etc.) Enhances modular design + reuse Streaming Applications Persistent compute structure (infrequent changes) Large data sets, mostly sequential access Limited feedback Implement with deep,system level pipelining E.g. DSP, multimedia JPEG Encoder: Ad Hoc Streaming Every module needs streaming flow control Block if inputs not available, output not ready to receive Every stream needs queueing Pipeline to match interconnect delay