现代逻辑设计英文试卷A_2014.docxVIP

中国计量学院2013 ~ 2014学年第2学期《 现代逻辑设计 》课程考试试卷（A）开课二级学院：信息工程学院 ，考试时间： 2014 年 6 月 日 时考试形式：闭卷□、开卷□，允许带 入场装订 线考生姓名： 学号： 专业： 班级： 题序一二三四五六七八九总分得分评卷人Fill in the blanks. (total 20/100, 2 for each blank)1、Y = (sel)?(A+B):(A- B); if the value of sel is 1，the result of Y is , otherwise the result of Y is . The operator “? :” is called _______________.2、The expand name of graphic file in Quartus II is and the expand name of waveform file is .3、The binary form of 8’h3f is ___________________.4、The general symbol of blocking statement is . The general symbol of non-blocking statement is .5、Assumed A=2’b11, B=4’b1001, the value of “{A,B}” is _________ , the value of “^b” is ________.二、Short-answer questions. (total 20/100)1、 In Verilog HDL，what’s the meaning of “always@(posedge clk)” and “always@(clk)”? (6/100)2、 Finite State Machine (FSM) can be divided into two types according to the generation of output values. What’s the difference between these two models? (6/100)3．Please explain the structure of a Verilog module with examples.(8/100)Give the definition of the variables and constants. (total 12/100, 3 for each)Define an 8-bit bus of wire type named “ABUS”.Define a 16-bit variable of reg type named “address”.装订线Define a parameter named “delay_time” which has the value of 8.Define a memory with the word width of 32 and memory size of 128.四、Program /dict_result.aspx?searchword=%e7%90%86%e8%a7%a3tjType=sentencestyle=t=comprehensioncomprehension. (total 16/100)1、Please correct the program of an 4-bit comparator which has two 4-bit inputs a and b and three outputs a_gt_b, a_eq_b and a_lt_b.（8/100）module 4bit_comp(a, b, a_gt_b, a_eq_b, a_lt_b);input[7:0] a, b;output a_gt_b, a_eq_b, a_lt_b;reg a_gt_b, a_eq_b, a_lt_b;assigna_gt_b=(ab),a_eq_b=(a=b),a_lt_b=(ab);endmoduleThis program is a 3-8 decoder which has an enable signal “en”. When “en” is logic 1, the decoder works in decoding mode. Fill in the blanks.(8/100)module decoder(a,y,en);input[2:0] a;input en;____