StratixV器件中的IO特性.pdf

Stratix V器件中的I/O特性 5 2014.01.10 SV51006 订阅 反馈 本章节详细说明了有关Stratix® V I/O单元(IOE)的特性以及IOE如何符合现有及新兴的I/O标准和要 求来进行操作。 Stratix V I/O支持以下功能： • 所有I/O bank 中的真LVDS通道支持SGMII、SPI-4.2和XSBI应用 • 器件所有侧带DPA 的I/O bank都支持硬核动态相位对齐(DPA)和串化器/解串器(SERDES) • 单端、非电压参考和电压参考I/O标准 • 低电压差分信号(LVDS)、RSDS、mini-LVDS、HSTL、HSUL和SSTL I/O标准在所有I/O bank上 • 双倍数据速率(DDR)、单倍数据速率(SDR)和半数据速率输入和输出选项 • 串化器/解串器(SERDES) • 高性能存储器接口的偏移校正、读写整平和时钟域交叉功能 • 可编程输出电流强度 • 可编程摆率 • 可编程总线保持 • 可编程上拉电阻 • 可编程预加重 • 可编程I/O延迟 • 可编程输出差分电压(VOD) • 开漏输出 • 带和不带校准的片上串行匹配(RS OCT) • 片上并行匹配(RT OCT) • 片上差分匹配(RD OCT) 注意: 本章节中的信息适用于所有Stratix V系列，除非另有说明。 相关链接 Stratix V器件手册: 已知问题 列出了对Stratix V器件手册章节所规划的更新。 © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at ISO /common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with 9001:2008 Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes Registered no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 101 Inn