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Asynchronous Synchronous Reset Design (异步和同步复位的设计)
Asynchronous & Synchronous Reset
Design Techniques - Part Deux
Clifford E. Cummings Don Mills Steve Golson
Sunburst Design, Inc. LCDM Engineering Trilobyte Systems
cliffc@ mills@ sgolson@
ABSTRACT
This paper will investigate the pros and cons of synchronous and asynchronous resets. It will
then look at usage of each type of reset followed by recommendations for proper usage of each
type.
1.0 Introduction
The topic of reset design is surprisingly complex and poorly emphasized. Engineering schools
generally do an inadequate job of detailing the pitfalls of improper reset design. Based on our
industry and consulting experience, we have compiled our current understanding of issues
related to reset-design and for this paper have added the expertise of our colleague Steve Golson,
who has done some very innovative reset design work. We continually solicit and welcome any
feedback from colleagues related to this important design issue.
We presented our first paper on reset issues and techniques at the March 2002 SNUG
conference[4] and have subsequently received numerous email responses and questions related
to reset design issues.
We obviously did not adequately explain all of the issues related to the asynchronous reset
synchronizer circuit because many of the emails we have received have asked if there are
metastability problems related to the described circuit. The answer to this question is, no, there
are no metastability issues related to this circuit and the technical analysis and explanation are
now detailed in section 7.1 of this paper.
Whether to use synchronous or asynchronous resets in a design has almost become a religious
issue with strong proponents claiming that their reset design technique is the only way to
properly approach the subject.
In our first paper, Don and Cliff favored
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