夏宇闻教材5(Xia Yuwen materials 5).doc

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夏宇闻教材5(Xia Yuwen materials 5)

夏宇闻教材5(Xia Yuwen materials 5) The fifth chapter introduces the basic arithmetic logic and their Verilog HDL model Preface The algorithm of digital logic circuit complex logic, by basic operation data flow control and interface logic circuit. A deep understanding of the basic logic is the basic algorithm design of complex logic circuit system structure. Although the Verilog hardware description language can help us to automatically synthesize combinational and sequential circuits is very complex, and help us to provide a comprehensive and detailed examination of the circuit, but for the special digital signal processing circuit speed is high, the structure or by the designer to decide. In order to improve the calculation speed of the algorithm in addition to improve the manufacturing technology, logic structure design is the most important link. And design the basic operation combination circuit structure is reasonable algorithm based on logical structure design, only in-depth understanding of many basic characteristics of complex combinational circuits, it is possible to improve the basic clock speed algorithm logic system by improving the circuit structure, a solid foundation for a digital logic system of the high speed complex algorithm reasonable structure of under the. This part of knowledge should be content about digital system and computer curriculum structure, in order to make students able to apply knowledge learned to design, it is necessary to improve the structure of the circuit principle and method of adders and multipliers speed simply review here, and the concept of pipeline design is also introduced in the this chapter. I hope the students can flexibly the basic concept of the application of these circuits to design, to improve the design level. 5.1 adder In the digital circuit course we have learned an adder circuit, namely full adder. It is easy to write the truth table, the circuit structure is simple and and not only a few. Xi Yi Ci-1 Si Ci 00000

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