suitability of various low-power testing techniques for ip core-based soc a survey各种低功耗测试技术的适用性ip为核心soc的一项调查.pdfVIP

Hindawi Publishing Corporation VLSI Design Volume 2011, Article ID 948926, 7 pages doi:10.1155/2011/948926 Review Article Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey Usha Mehta,1 Kankar Dasgupta,2 and Niranjan Devashrayee1 1 PG-VLSI Design Group, EC Department, Institute of Technology, Nirma University, Ahmedabad 382 481, India 2 Space Application Centre, Indian Space Research Organization, Ahmedabad 380 015, India Correspondence should be addressed to Usha Mehta, usha.mehta@nirmauni.ac.in Received 3 September 2010; Accepted 23 December 2010 Academic Editor: Yangdong Deng Copyright © 2011 Usha Mehta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Test power is the major issue for current generation VLSI testing. It has become the biggest concern for today’s SoC. While reducing the design efforts, the modular design approach in SoC (i.e., use of IP cores in SoC) has further exaggerated the test power issue. It is not easy to select an effective low-power testing strategy from a large pool of diverse available techniques. To find the proper solutions for test power reduction strategy for IP core-based SoC, in this paper, starting from the terminology and models for power consumption during test, the state of the art in low-power testing is presented. The paper contains the detailed survey on various power reduction techniques proposed for all aspects of testing like external testing, Built-In Self-Test techniques, and the advances in DFT techniques emphasizing low power. Further, all the available low-power testing techniques are strongly analyzed for their suitabi