ddr3与ddr2的不同之处（The difference between DDR3 and DDR2）.docVIP

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ddr3与ddr2的不同之处（The difference between DDR3 and DDR2）.doc

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ddr3与ddr2的不同之处（The difference between DDR3 and DDR2）

ddr3与ddr2的不同之处（The difference between DDR3 and DDR2） The difference between DDR3 and DDR2 1, logical Bank quantity DDR2 SDRAM has 4Bank and 8Bank design, the purpose is to meet the needs of future large capacity chip. And DDR3 is likely to start from the 2Gb capacity, so the initial logical Bank is 8, and is ready for the next 16 logical Bank. 2, package (Packages) DDR3 due to the addition of a number of features, so in terms of pin will be increased, 8bit chip using 78 ball FBGA package, 16bit chip using 96 ball FBGA package, and DDR2 has 60/68/84 ball, FBGA package three specifications. And DDR3 must be green package, not containing any harmful substances. 3, burst length (BL, Burst, Length) Because the DDR3 prefetching is 8bit, so the burst transmission cycle (BL Burst Length) is fixed to 8, and for DDR2 and early DDR system, BL=4 is also used, so DDR3 added a 4-bit Burst Chop (burst mutation) mode, burst data transmission from a BL=4 read operation plus write a BL=4 to synthesize a BL=8, then through the A12 address line to control the burst mode. Also, it is important to point out that any burst interrupt operation will be prohibited in DDR3 memory and will not be supported and replaced by more flexible burst transport control (such as 4bit sequential burst). 3, addressing timing (Timing) Just as the number of delay cycles increases after the transition from DDR to DDR2, the CL cycle of DDR3 will also be higher than that of DDR2. The CL range of DDR2 is generally between 2 and 5, while DDR3 is between 5 and 11, and the design of additional delay (AL) has also changed. In DDR2, AL ranges from 0 to 4, while DDR3 has three options at AL: 0, CL-1, and CL-2. In addition, DDR3 adds a new time parameter called write delay (CWD), which is based on the specific frequency of the work. 4, new function - reset (Reset) The reset is an important feature added by DDR3, and a pin is specifically prepared for this purpose. DRAM industry has long been required to increase this f