51单片机中断（51 singlechip interrupt）.docVIP

51单片机中断（51 singlechip interrupt） Say the most basic, the old 51 single chip microcomputer (80C51 Series) has 5 interrupt source, 2 priority, can achieve two levels of interrupt service nesting. Many expanded 51 microcontrollers now have 4 priority levels (or more) and more interrupt sources. Before talking about interruption, I first define the priority, understand what the priority is, and the later statement is easy to understand. In fact, many people are confused about the priority of meaning, so that in disorderly fashion. There are two priority levels for the interrupt: query priority and execution priority. What is the optimal query? The default we see from the datasheet or the book (the IP register is not set, the power on reset is 00H) priority: external interrupt 0 timer / counter 0 external interrupt 1 timer / counter 1 serial interrupt Or INT0, timer0, INT1, Timer1, serial, port or INT0, T0, INT1, T1, UART, or PX0PT0PX1PT1PS...... Is the query quality. First, the query priority cannot be changed and set. This is a problem of queuing priority with interruption. When multiple interrupt sources interrupt the signal at the same time, the interrupt arbiter selects the order in which interrupt source priority should be processed. This does not have anything to do with the interruption of the nesting of service programs. When the CPU query interrupt flag all the time, will be in accordance with the above 5 query priority order query, when the number of interrupt requests at the same time, will give priority to the high quality query query first level interrupt flag, but does not represent a high priority interrupt query can interrupt the already low priority and executing the query interrupt service. For example: when the counter 0 interrupt and 1 (according to the query priority, counter 0 external interrupt interrupt 1) when they arrive at the same time, will enter the timer 0 interrupt service function; but in the external interrupt interrupt service fun