01_静态时序分析基本原理和时序分析模型.pdfVIP

® Quartus® II Software Design Quartus II Software Design Series: Timing Analysis Series: Timing Analysis - Timing analysis basics - Timing analysis basics © 2009 Altera Corporation 1 Objectives Objectives Display a complete understanding of timing analysis © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 2 How does timing verification work? How does timing verification work? Every device path in design must be analyzed with respect to timing specifications/requirements − Catch timing-related errors faster and easier than gate-level simulation board testing Designer must enter timing requirements exceptions − Used to guide fitter during placement routing − Used to compare against actual results PRE PRE IN D Q D Q OUT CLK CLR CLR CLR combinational delays © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 3 Timing Analysis Basics Timing Analysis Basics Launch vs. latch edges Setup hold times Data clock arrival time Data required time Setup hold slack analysis I/O analysis Recovery removal Timing models © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 4 Path Analysis Types Path Analysis Types Async Path