VHDL状态机.docVIP

单进程设计方法 library ieee; use ieee.std_logic_1164.all; entity memory_controller is port(ready,clk,read_write : in std_logic; we,oe : out std_logic); end memory_controller; architetrue state_machine of memory_controller is type state_type is (idle,decision,read,write); singal state :state_type; begin process(clk) begin if(clkevent and clk=1) then case state is when idel= if(ready=1) then state=decision; Else state=idle; End if; When decision= if(read_write=1) then state=read; Else state=write; End if; When read= if(ready=1) then state=idle; Else state=read; When write= if(ready=1) then state=idle; Else state=write; End if; end case; end if; end process; oe=1 when state=read else 0; we=1 when state=write else ‘0’; end state_machine; 双进程设计方法之一 library ieee; use ieee.std_logic_1164.all; entity memory_controller is port(ready,clk,read_write : in std_logic; we,oe : out std_logic); end memory_controller; architetrue state_machine of memory_controller is type state_type is (idle,decision,read,write); singal present_state ,next_state :state_type; begin process(present_state,ready,read_write) begin case present_state is when idel= we=0;oe=0; If(ready=1) then next_state=decision; else next_state=idle; end if; when decision= we=0;oe=0; if(read_write=1) then next_state=read; else next_state=write; end if; when read= we=0;oe=1; if(ready=’1’) then next_state=idle; else next_state=read; when write= we=1;oe=0; if(ready=1) then next_state=idle; else next_state=write; end if; end case; end process; process(clk) begin if(clkevent and clk=1) then present_stat