Lesson 35 Cadence 电子技术专业英语教程[冯新宇主编][电子教案].ppt

《电子技术专业英语教程》 * Unit 12 EDA Tools Lesson 35 Cadence 《电子技术专业英语教程》冯新宇 主编 电子工业出版社 * * Lesson 35 Cadence Backgrounds Text tour Language in use Vocabulary Structure Reading/writing techniques * * Terminology full custom behavioral simulation mixed-signal, SoC wire delay, DSM timing-driven Backgrounds * * Terminology * * Cadence is known for its full custom IC design ability, which includes tools such as Virtuoso Schematic Composer, Affirma Analog Design Environment, Virtuoso Layout Editor, Affirma Spectra, Virtuoso Layout Synthesizer, Assura Verification Environment, and Dracula and so on. Cadence以它全定制集成电路设计能力著称，包括Virtuoso Schematic Composer, Affirma Analog Design Environment, Virtuoso Layout Editor, Affirma Spectra, Virtuoso Layout Synthesizer, Assura Verification Environment, Dracula等工具。 full custom * * Then we do behavioral simulations with the tools such as Verilog-XL, NC-verilog, Leapfrog VHDL, and NC-VHDL etc. to estimate the design, verify the modules function, and debug the project. 然后我们应用Verilog-XL，NC-verilog，Leapfrog VHDL和NC-VHDL工具进行行为仿真，评估设计，验证模块功能，调试工程。 behavioral simulation * * Nowadays, many types of software take the wire delay into account right in the floor plan phase. It is also the demand of the Deep Sub Micron (DSM) design. 现如今，许多软件在预布局阶段就考虑连线延迟。这也是深亚微米设计的需要。 wire delay, DSM (deep sub-micron) * * Timing Driven DSM Design Tools 时序驱动的深亚微米设计工具 timing-driven * * Outline Overview (para.1, 2, 3) Full Custom IC Design Tools(para.4, 5) Getting Started with MATLAB (para.6, 7) Link to EDA simulator (para.8, 9, 10, 11) Text tour * * Introduction to Cadence Company Cadence EDA tools Overview of Cadence Cadence tools * * Unix login icfb Full Custom IC Design Tools CIW of icfb * * Logic design flow LDV Logic Design and Verification Tools * * Tools for lower level design wire delay and DSM design Timing Driven DSM Design Tools * * Vocabulary * * To come, exist, or occur before in time. 先于…：先于…之前出现、存在或发生 To come before in order or ra