低复杂度先进密码算法的VLSI实现.pdfVIP

33 4 2007 2 Vol.33 No.4 Computer Engineering February 2007 ·· 2007 A TP301 VLSI ( 200433) (AES)VLSI AES (SubByte) HHNEC 0.25 m CMOS 100MHz 128bits 800Mps 30K AES VLSI Implementation of Low Cost AES Algorithm CHEN Jun, WANG Jing, ZENG Xiaoyang, HAN Jun (State Key Lab of ASIC and System, Fudan University, Shanghai 200433) AbstractThis paper proposes a compact and low cost architecture for AES encrypt and decrypt. As the mathematical manipulation lies on finite filed computation, the orders of the round operation are modified so that the design can reuse some modules to save the area. Meanwhile the element inversion in the SubByte module is performed by composite field technique and the area and power consumption is reduced significantly. Based on the HHNEC 0.25 m CMOS technology, area of the design is about 30k equivalent gates and its system frequency will be up to 100MHz. The operation speed of the 128bits data encryption and decryption is as high as 800Mbps. Key wordsAES; Low cost; SubByte; Composite field AES AES [4,6] Gbps 1 0 [5] RFID