[计算机软件及应用]第4章VHDL设计实例.ppt

第四章;组合逻辑电路设计 时序逻辑电路设计 存储器设计 状态机设计;一、4选1多路选择器 ;LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY mux4 IS PORT (a,b,c,d,s0,s1: IN std_logic; y: OUT std_logic ); END mux4; ARCHITECTURE func OF mux4 IS VARIABLE sel:std_logic_vector(1 DOWNTO 0)； BEGIN sel=s1s0; y = a WHEN sel =‘00 ELSE b WHEN sel =‘01’ ELSE c WHEN sel =‘10’ ELSE d WHEN sel =‘11’ ELSE ‘X’; END func; ;;LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY encoder8_3 IS PORT (d: IN std_logic_vector(7 downto 0); y0,y1,y2: OUT std_logic ); END encoder8_3; ARCHITECTURE func OF encoder8_3 IS BEGIN PROCESS(d) VARIABLE temp:std_logic_vector(2 downto 0); BEGIN IF(d(7)=‘1’) THEN temp:=“111”; ELSIF(d(6)=‘1’) THEN temp:=“110”;; ELSIF(d(5)=‘1’) THEN temp:=“101”; ELSIF(d(4)=‘1’) THEN temp:=“100”; ELSIF(d(3)=‘1’) THEN temp:=“011”; ELSIF(d(2)=‘1’) THEN temp:=“010”; ELSIF(d(1)=‘1’) THEN temp:=“001”; ELSIF(d(0)=‘1’) THEN temp:=“000”; END IF y(0)=temp(0); y(1)=temp(1); y(2)=temp(2); END PROCESS END func;;普通8-3编码器;;LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY decoder3_8 IS PORT (a2,a1,a0,g1,g2a,g2b: IN std_logic; y: OUT std_logic_vector); END decoder3_8; ARCHITECTURE func OF decoder3_8 IS BEGIN PROCESS(a2,a1,a0,g1,g2a,g2b) VARIABLE temp:std_logic_vector(2 downto 0); BEGIN temp:=a2a1a0; IF(g1=‘1’and g2a=‘0’and g2b=‘0’)THEN; CASE temp IS WHEN “000”=y= WHEN “111”=y=; WHEN “OTHERS”=y=“XXXXXXXX”; END CASE; ELSE y= END IF; END PROCESS; END func;;三：加法器;LIBRARY IEEE; --半加器描述 USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder IS PORT (a, b : IN STD_LOGIC; co, so : OUT STD_LOGIC); END h_adder; ARCHITECTURE fh1 OF h_adder is BEGIN so = NOT(a XOR (NOT b)) ; co = a AND b ; END fh1; ;全加器f_adder电路图及其实体模块 ; LIBRARY IEEE; --1位二进制全加器顶层设计描述 USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_adder IS PORT (ain，bin，cin : IN