基于VHDL的IIC时序电路设计.docVIP

基于VHDL的IIC时序电路设计 iic 总线在设计时要看你所使用的器件的传输或接收时序只要会一个，其他的都一样以下是我在一本书上看到的，你看看就会用了library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity reciver isport(reset,clk:in std_logic;sda,scl:inout std_logic;rd:out std_logic;tdata:in std_logic_vector(7 downto 0);rdata:out std_logic_vector(7 downto 0));end reciver;architecture one of reciver issignal rdatai:std_logic_vector(7 downto 0);type state is (start,transmit,ack,sub,ack1,start1,slave,ack2,reading,ack3);signal current:state;beginprocess(clk,reset)variable count:integer range 0 to 40;variable cnt:integer range 0 to 8;beginif reset=1thensda=1;scl=1;rdatacurrent=start;cnt:=8;count:=0;elsif clkevent and clk=1 thencase current iswhen start=count:=count+1;case count iswhen 1=sda=1;when 2=scl=1;when 3=sda=0;when 4=scl=0; when 10=count:=0;current=transmit;when others=null;end case;when transmit=count:=count+1;case count iswhen 1=sda=tdata(cnt);when 2=scl=1;when 3=scl=0;when 4=cnt:=cnt-1;count:=0;if cnt=0 then cnt:=8;current=ack;rd=1;else current=transmit;rd=0;end if;when others=null;end case;when ack=count:=count+1;case count iswhen 1=sda=0;when 2=scl=1;when 3=scl=0;when 4=current=sub;count:=0;when others=null;end case;when sub=count:=count+1;case count iswhen 1=sda=tdata(cnt);when 2=scl=1;when 3=scl=0;when 4=cnt:=cnt-1;count:=0;if cnt=0 then cnt:=8;current=ack1;rd=1;else current=sub;rd=0;end if;when others=null;end case;when ack1=count:=count+1;case count iswhen 1=sda=0;when 2=scl=1;when 3=scl=0;when 4=current=start1;count:=0;when others=null;end case;when start1=count:=count+1;case count iswhen 1=sda=1;when 2=scl=1;when 3=sda=0;when 4=scl=0;when 5=current=slave;count:=0;when others=null;end case;when slave=count:=count+1;case count iswhen 1=sda=tdata(cnt);when 2=scl=1;when 3=scl=0;when 4=cnt:=cnt-1;count:=0;if cnt=0 then cnt:=8;current=ack2;rd=1;else current=sub;rd=0;end if;when