毕业设计雷晓勇.docVIP

浙 江 理 工 大 学 毕业论文(设计)诚信声明 我谨在此保证：本人所写的毕业论文(设计)，凡引用他人的研究成果均已在参考文献或注释中列出。论文(设计)主体均由本人独立完成，没有抄袭、剽窃他人已经发表或未发表的研究成果行为。如出现以上违反知识产权的情况，本人愿意承担相应的责任。 声明人(签名)： 年 月 日 摘 要 MCS-51单片机是在一块芯片中集成了CPU、RAM、ROM、定时器/计数器和多功能I/O等一台计算机所需要的基本功能部件，是业界广泛使用的单片机系列。基于FPGA平台的8051单片机CPU核与传统MCS-51单片机完全兼容，但速度约为传统单片机的 20倍，且在FPGA内可轻松的集成许多高性能系统功能，这将使系统的设计效率和系统性能获得极大的提高，这也是现代电子设计技术的发展方向。从CPU的总体结构到局部功能的实现采用了自顶向下的设计方法和模块化的设计思想，利用FPGA，设计实现了八位CPU核。Verilog HDL； CPU； FPGA ABSTRACT MCS-51 MCU is a single chip integrated CPU, RAM, ROM, timer / counters and multi-function I / O such as a computers basic features required, is the industrys widely used microcontroller series. 8051 FPGA-based CPU platform with the traditional core is fully compatible with MCS-51 microcontroller, but the speed is about 20 times that of traditional single chip, and the FPGA can be easily integrated within a number of high-performance system functions, which will enable the design of the system efficiency and system Be greatly improved performance, which is the development of modern electronic design direction. The issue with the hardware description language design MCS-51 CPU core, from the CPU to the local function of the overall structure of the realization of using top-down design and modular design, the use of FPGA, design and implementation of the eight CPU cores. The CPU model in this paper can execute the MCS-51MCU assemble language instruction sets, and is better than the traditional MCS-51 MCU on both clock frequency and the execution efficiency of the instruction. This design was existed in a form of HDL source code，which can be reused in many SoC designs．This model can be read easily, updated easily and extended freely, so it has a practical value in SoC design．This design was implemented on FPGA. Keywords: Verilog HDL ； CPU ； FPGA 第1章 绪论 ...1 1.1选题背景……………………………………………………………………………………1 1.2国内外发展及现状…………………………………………………………………………1 1.3课题的主要内容……………………………………………………………………………2 第2章CPU的结构及设计…………………………………………………