XilinxFPGA结构幻灯片.ppt

Spring 2003 Xilinx FPGA Anselmo Lastra Topics FPGA internals Clock management Chipscope State Machines Design What if we were using a font that’s 10 high, but 2 of the rows are always blank? How about a given number of fixed-size sprites anywhere on the screen? Xilinx FPGA Internals Spartan2 4K bit RAM blocks Large amt of logic Program stored in SRAM Switch Matrix Pass Transistor Mux Controlled by Memory Logic Lookup Table Instead of gates So doesn’t matter much how you specify your logic Ends up truth table Xilinx CLB Spartan 2 At right two logic cells (LC) Two (four LCs) in CLB LUT is small RAM Can be used as RAM CLB Muxes can make full 6-input function Can generate some functions w/ up to 19 inputs Each LC can be 1 bit of an adder Xilinx IOB Spartan 2 IOB RAM Ours has 10 blocks for a total of 40Kbits SRAM Delay Lock Loops Circuitry to Synchronize internal clock to external clock Divide the clock Instead of how you were counting it Run the clock over low skew lines Double the clock frequency There are four on our chips Clock Synchronization Set internal to one cycle behind external Effectively clock edges are aligned Clock Division and Sync //synthesis attribute CLKDV_DIVIDE of dll is 8 //synopsys translate_off defparam dll.CLKDV_DIVIDE = 8; //synopsys translate_on CLKDLL dll (.CLKIN(CLKIN), .CLKFB(CLK0), .RST(RESET), .CLK0(CLK0), .CLK90(), .CLK180(), .CLK270(), .CLK2X(), .CLKDV(DIV), .LOCKED(LOCKED)); CLKIn is input clock CLK0 is locked (indicated by LOCKED) DIV is divided by the CLKDV_DIVIDE factor Clock Division Example Here was set to divide-by-4 Practical Matters Have found that clock DLL divisor only works reliably if you initialize it with reset Our Device Specs See /bvdocs/publications/ds001_2.pdf Spartan 3 Virtex-II Virtex-II Pro Links Link page on course web Hardware documentation Application notes on Xilinx web page Info on DLL /bvdocs/appnotes/xapp174.pdf /bvdocs/appnotes/xapp132.pdf Next Chipscope State Machines Design What if we were using a fo