高速高精度采样保持电路理论模型与技术实现-theoretical model and technical implementation of high-speed and high-precision sample-and-hold circuit.docx

ABSTRACTABSTRACTSample and Hold (S/H) circuit is the key front-end block of Analog-to-Digital converters (ADCs), while ADCs are of importance in modern VLSI digital signal processing systems. The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires ADCs with a higher sampling rate, higher resolution, and lower power consumption. Hence the same performance requirements come to the S/H circuits.This thesis studies the academic models and technical implementation schemes for high speed, high resolution S/H circuits. It covers the S/H architecture, the relationship between S/H and Pipeline ADC, sampling switch with error sources, double sampling, and optimization on settling features of operational amplifier. Finally, a 12bit 100MSample/s S/H prototype circuits is designed based on SMIC 0.18μm CMOS mixed-signal process. The details include:The main architectures of S/H circuits are discussed, and it specifies that the switched capacitor close-loop flip-over S/H topology can achieve 12bit 100MSample/s performance under sufficient reliability and realizability.The relationship between pipeline ADC architecture and S/H performances is examined, especially on noise-power trade-off. The sampling capacitor value and the input offset voltage of Op-Amp are specified, with the consideration of the noise transfer function and tolerance, stage resolution distribution theory in pipeline ADC and process mismatch.Established the equivalence circuit and error sources model of sampling switches, where the later emphasizes the charge injection, nonlinear analog bandwidth and sampling moment uncertainty. Then the error-corresponding performance-improved circuits are examined. The circuits and error sources are analyzed in both time and frequency domain with Matlab simulation environment. The results show that: 0.637ps clock rms jitter brings -120dB noise to the S/H; the full differential boots