Fast Buffer Memory with Deterministic Packet Departures：确定数据包离开高速缓冲存储器.pptVIP

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Fast Buffer Memory with Deterministic Packet Departures：确定数据包离开高速缓冲存储器.ppt

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Fast Buffer Memory with Deterministic Packet Departures：确定数据包离开高速缓冲存储器

Spring 2005 044114 Fast Buffer Memory with Deterministic Packet Departures Mayank Kabra, Siddhartha Saha, Bill Lin University of California, San Diego Packet Buffer in Routers Incoming linecards have 40byte@40Gbps = 8ns to read and write a packet. The routers need to store the packets to deal with congestion. Bandwidth X RTT = 40Gb/s*250ms = 1Gb buffer. Too big to store in SRAM, hence need to use DRAM. Problem: DRAM access time ~40ns. So, there is roughly 10x speed difference. Parallel and Interleaved DRAM banks Assume the speed difference is 3x Problems with Parallelism The access pattern can create problems. If we try to access 3, 6, 9 and 11 one after another, it is possible to issue interleaved read requests and read those packets out at Line Speed. Problems with Parallelism But, accessing 2 3 or 10 11 in succession is problematic. This is an example of a Bank Conflict Use The Packet Departure Time Wide classes of routers (Crossbar Routers) where the packets departures are determined by the scheduler on the fly. Packet buffers which cater to these routers exist but are complex There are other high performance routers such as Switch-Memory-Switch, Load Balance Routers for which packet departure time can be calculated when the packet is inserted in the buffer. Packet Buffer Abstraction Fixed sized packets, time is slotted (Example: 40Gb/s, 40 byte packet = 8ns). The buffer may contain arbitrary large number of logical queues, but with deterministic access. Single-write Single-read time-deterministic packet buffer model. Packet Buffer Architecture Interleaved memory architecture with multiple slower DRAM banks. K slower DRAM banks. b time slots to complete a single memory read or write operation. b consecutive time slots is a frame. A time slot t belongs to frame [t/b] Packet Buffer Operation Packet Arrival [Frame 1] Frame 1: Assume b = 3 Packets P1, P2 P3 arrive in time slot 1, 2 and 3 respectively. They are aggregated before writing to the DRAM.