第四章vhdl顺序语句sequentialstatement.pptxVIP

4.1、SIGNAL a,b,c,d : STD_LOGIC;SIGNAL S : STD_LOGIC_VECTOR(1 TO 4);…VARIABLE e, f : STD_LOGIC;VARIABLE g : STD_LOGIC_VECTOR(1 TO 2);VARIABLE h : STD_LOGIC_VECTOR(1 TO 4);S =(‘0’, ‘1’, ‘0’ , ‘0’);(a, b, c, d) = s;--a=‘0’; b=‘1’; c=‘0’; d=‘0’; …(3=e, 4=f, 2=g(1), 1=g(2) ):=h;--g(2) :=h(1) ; g(1) :=h(2) ; e :=h(3) ; f :=h(4) ;4.2求取最大值 BEGIN IF (ab) THEN y=b; ELSE y=a; END IF; END max;B用VHDL设计一个D触发器ddf1引进内部节点信号进程和敏感信号检测CLK上升沿顺序语句将数据输出端口PROCESS (clock, clear)BEGIN IF clear = ‘0’ THEN q = ‘0’; ELSIF clock’EVENT and clock = ‘1’ THEN q = d; END IF;END PROCESS;T触发器Process(clk)begin if(clk’event and clk=‘1’) then if(t = ‘1’) then q = not(q); else q = q; end if; end if;end process;ENTITY mul IS PORT (a, b, sel : IN BIT; data_out : OUT BIT);END mul;ARCHITECTURE ex OF mul ISSIGNAL temp : BIT;BEGIN process_a: PROCESS (a, b, selx) BEGIN IF (sel = ‘0’) THEN temp = a; ELSE temp = b; END IF; data_out = temp; END PROCESS process_a;选择S1,s22azbmuxcdLIBRARY ieee;USE ieee.std_logic_1164.all; ENTITY mux41 isPORT (s1,s2,a,b,c,d : IN STD_LOGIC; z : OUT STD_LOGIC); END mux41;ARCHITECTURE activ OF mux41 IS SIGNAL s : STD_LOGIC_VECTOR( 1 DOWNTO 0); BEGIN s= s1s2 ; PROCESS (s ,a,b,c,d) BEGIN CASE s IS WHEN “00” = z= a; WHEN “01” = z= b; WHEN “10” = z= c; WHEN “11” = z= d; WHEN OTHERS =z= ‘x’; END CASE; END PROCESS;END activ;8位奇偶校验电路ENTITY p_check isPORT (a : IN STD_LOGIC_VECTOR(7 DOWNTO 0); Y : OUT STD_LOGIC); END p_check ;ARCHITECTURE opt OF p_check IS SIGNAL tmp : STD_LOGIC; BEGIN PROCESS (a) BEGIN tmp= ‘0’; 过程（PROCEDURE）函数（FUNCTION）VHDL的子程序有两种类型：四、子程序调用语句子程序的特点：----子程序可以在结构体的任何位置被调用，而且可以反复调用。 过程（PROCEDURE）过程语句的结构： PROCEDURE 过程名（形式参数1；形式参数2；… ）IS [定义语句]； BEGIN [顺序处理语句]； END 过程名；过程语句的调用格式： 过程名 [（[形数名= ]实参表达式 {，[形数名= ]实参表达式}）]；PACKAGE data_type ISsubtype data_element is integer range 0 to 3 ;type data_array is array (1 to 3) of data_element;end data_type;use work.data_type.all;ENTITY sort isPORT (in_array : indata_array ; out_array : out