微机原理ch02 THE 80x86 MICROPRCESSOR.docVIP

PAGE 21 THE 80x86 MICROPROCESSOR BRIEF HISTORY OF THE 80x86 FAMILY 表 STYLEREF 1 \s 2 SEQ 表 \* ARABIC \s 1 1 Evolution of Intel’s Microprocessors Product 8080 8085 8086 8088 80286 80386 80486 Year introduced 1974 1976 1978 1979 1982 1985 1989 Clock rate (MHz) 2-3 3-8 5-10 5-8 6-16 16-33 25-50 No. transistors 4500 6500 29,000 29,000 130,000 275,000 1.2 million Physical memory 64K 64K 1M 1M 16M 4G 4G Internal data bus 8 8 16 16 16 32 32 External data bus 8 8 16 8 16 32 32 Address bus 16 16 20 20 24 32 32 Datatype (bits) 8 8 8,16 8,16 8,16 8,16,32 8,16,32 INSIDE THE 8088/8086 图 STYLEREF \s 标题 1 2 SEQ 图 \* ARABIC \s 1 1 Internal Block Diagram of the 8088/86 CPU Pipelining 流水线操作 图 STYLEREF \s 标题 1 2 SEQ 图 \* ARABIC \s 1 2 Pipelined vs. Non-pipelined Execution Intel implemented the concept of pipelining in the 8088/86 by splitting the internal structure of microprocessor into two sections: the execution unit (EU) and the bus interface unit (BIU). The BIU accesses memory and peripherals while the EU executes instructions previously fetched. This works only if BIU keeps ahead of the EU, thus the BIU of the 8088/86 has a buffer. The buffer is 4 bytes long in the 8088 and 6 bytes in the 8086. If any instruction takes too long to execute, the queue is filled to its maximum capacity and the bus will set idle. The BIU fetches a new instruction whenever the queue has room for 2 bytes in the 6-byte 8086 queue, and for 1 byte in the 4-bytes 8088 queue. Pipelining in the 8088/86 has two stages: fetch and execution. Registers In the CPU, register are used to store information temporarily. 图 STYLEREF \s 标题 1 2 SEQ 图 \* ARABIC \s 1 3 register 表 STYLEREF 1 \s 2 SEQ 表 \* ARABIC \s 1 2 Registers of the 8086/286 by Category Category Bits Register Name General 16 AX, BX, CX, DX 8 AH, AL, BH, BL, CH, CL, DH, DL Pointer 16 SP (stack pointer) BP (base pointer) Index 16 SI (source index) DI (destination index) Segment 16 CS (code segment) DS (data segment) SS (stack segment) ES (e