超大规模集成电路第九次作业2016秋,段成华.docxVIP

Assignment 9 1. Design an 8-bit up and down synchronous counter in VHDL with the following features: The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered (three-state). The counter is with an asynchronous reset that assigns a specific initial value for counting. The counter is with a synchronous data load control input for a new value of counting and an enable control input for allowing the up and down counting. The load control input has a priority over the enable control input. This implies that when the load operation is in process the counter operation is prohibited. Some data types, such as STD_LOGIC, UNSIGNED, SIGNED and INTEGER, may be used. Synthesize the design. Create a set of reasonable input waveforms for your design and complete both behavioral and post-placeroute simulations with internal signals and/or variables included in waveform or list windows. Solution:代码如下： library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity count_8_bidir is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; load : in STD_LOGIC; enable : in STD_LOGIC; cnt : inout STD_LOGIC_VECTOR (7 downto 0)); end count_8_bidir; architecture Behavioral of count_8_bidir is signal cnt_in: STD_LOGIC_VECTOR (7 downto 0); signal cnt_out: STD_LOGIC_VECTOR (7 downto 0); begin pro0:process(oe,cnt_out,cnt) begin if(load=1)then cnt = (others=Z); cnt_in = cnt; else cnt = cnt_out; end if; end process; pro1:process(clk,rst) begin if(rst=1)then cnt_out = (others=0);