数字系统课程设计—vhdl.pptVIP

Moore型状态机 ARCHITECTURE behave OF moore_example IS TYPE state_type IS ( s1,s2,s3,s4); SIGNAL state: state_type; BEGIN PROCESS (clk, reset ) IF reset=‘1’ THEN state=s1; ELSIF ( clk’event and clk=‘1’) THEN CASE state IS WHEN s1=IF datain=‘1’THEN state=s2;END IF; WHEN s2=IF datain=‘0’THEN state=s3;END IF; Moore型状态机 WHEN s3=IF datain=‘1’THEN state=s4;END IF; WHEN s4=IF datain=‘0’THEN state=s1;END IF; END CASE; END IF; END PROCESS; PROCESS (state) BEGIN CASE state IS WHEN s1=dataout=“0001”; Moore型状态机 WHEN s2=dataout=“0010”; WHEN s3=dataout=“0100”; WHEN s4=dataout=“1000”; END CASE; END PROCESS; END behave; Mealy型状态机 S1 S2 S3 S4 1－0001 0－0000 1 0 1 0 0－0010 1－0001 1－0100 0－0001 0－1000 1－0001 Mealy型状态机 LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY mealy_example IS PORT (clk, datain, reset : IN std_logic; dataout: OUT std_logic_vector(3 downto 0)); END mealy_example; Mealy型状态机 ARCHITECTURE behave OF mealy_example IS TYPE state_type IS ( s1,s2,s3,s4); SIGNAL state: state_type; BEGIN PROCESS (clk, reset ) IF reset=‘1’ THEN state=s1; ELSIF ( clk’event and clk=‘1’) THEN CASE state IS WHEN s1=IF datain=‘1’THEN state=s2;END IF; WHEN s2=IF datain=‘0’THEN state=s3;END IF; Mealy型状态机 WHEN s3=IF datain=‘1’THEN state=s4;END IF; WHEN s4=IF datain=‘0’THEN state=s1;END IF; END CASE; END IF; END PROCESS; PROCESS (state) BEGIN CASE state IS WHEN s1=IF datain=‘1’ THEN dataout=“0001”; ELSE dataout=“0000” END IF; Mealy型状态机 WHEN s2=IF datain=‘0’ THEN dataout=“0010”; ELSE dataout=“0001”; END IF; WHEN s3=IF datain=‘1’ THEN dataout=“0100”; ELSE dataout=“0001”; END IF; WHEN s4=IF datain=‘0’ THEN dataout=“1000”; ELSE dataout=“0001”; END IF; END CASE; END PROCESS; END behave; VHDL设计FPGA的基本方法 1.文本编辑:用任何文本编辑器都可以进行,也可以用专用的HDL编辑环境.VHDL文件保存为.vhd文件. 2.逻辑综合与布局布线:使用综合器和布局布线工具对文件进行处理. 3.仿真:利用仿真软件验证电路的功能和时序. 4.编程下载：确认仿真无误后,将文件下载到芯片中. 一个实例 以一个十字路口交通