设计初步新模版.ppt

《数字电路与系统设计》EDA实验 VHDL设计初步 1 多路选择器的VHDL描述 1 多路选择器的VHDL描述 1 多路选择器的VHDL描述 1 多路选择器的VHDL描述 补充 WITH …. SELECT 语句 用WITH …. SELECT语句描述2选1多路选择器 Finite State Machine (FSM) - State Diagram Writing VHDL Code for FSM To Determine Next State Transition/Logic: Use a CASE Statement Inside IF-THEN Statement That Checks for the Clock Condition Remember: State Machines Are Implemented Using Registers To Determine State Machine Outputs: Use Conditional and/or Selected Signal Assignments Or Use a Second Case Statement to Determine the State Machine Outputs FSM VHDL Code - Enumerated Data Type FSM VHDL Code - Next State Logic FSM VHDL Code - Outputs FSM VHDL Code - Outputs Using a Case 习 题 习 题 习 题 习 题 习 题 习 题 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY statem IS PORT ( clk : IN std_logic; x,reset : IN std_logic; z : out std_logic ); END statem; 0/1 1/0 1/0 sa 1/0 0/0 0/0 0/0 sb sc sd x/z 1/0 例： “1110”序列检测器设计 ARCHITECTURE behave OF statem IS TYPE STATE_TYPE IS (sa, sb, sc,sd); SIGNAL state: STATE_TYPE; BEGIN PROCESS (clk,reset) BEGIN IF reset = 1 THEN state = sa; ELSIF clkEVENT AND clk = 1 THEN CASE state IS WHEN sa = IF x=1 THEN state = sb; ELSE state=sa; END IF; WHEN sb = IF x=1 THEN state = sc; ELSE state=sa; END IF; WHEN sc = IF x=1 THEN state=sd; ELSE state=sa; END IF; WHEN sd = IF x=1 THEN state = sd; ELSE state=sa; END IF; END CASE; END IF; --reset END PROCESS； z=1 when state=sd and x=‘0 else 0; END ARCHITECTURE behave; 0/1 1/0 1/0 sa 1/0 0/0 0/0 0/0 sb sc sd x/z 1/0 RESET nw = 1 Tap1 select = 0 first = 1 Idle nxt = 0 first = 0 Tap2 select = 1 first = 0 Tap3 select = 2 Tap4 select = 3 nxt = 1 nw = 1 nw = 0 Inputs: reset nw Outputs: select first nxt RESET nw = 1 Tap1 select = 0 first = 1 Idle nxt = 0 first = 0 Tap2