逻辑信号电平测试器的设计.doc

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6 - 7 - 孙琪:逻辑信号电平测试器的设计 1 逻辑信号电平测试器的设计 摘要 本文介绍了一个逻辑信号电平测试器,它可以方便快捷的测量某一点的电位的高低,通过声音的有无和声音的频率来判定被测电位的电平范围,从而能解决平常对电路中某点的逻辑电平进行测试其高低电平时,采用很不方便的万用表或示波器等仪器仪表的麻烦。该电路主要包括三部分电路:输入电路、逻辑状态识别电路和音响声调产生电路。其主要应用了集成运放的非线性电路特性,开环增益很大,从而可以制作成双限比较器;用555定时器构成的多谐振荡器作为音响产生电路,利用对电容的充放电,得到一定频率的信号。输入的逻辑信号电平大于或小于所设定的高低电平电位,则音响电路发声,如若在高低电平之间,则音响电路不发声。利用这种方式设计电路,计算元器件参数,选择成本合适的器件,确定电路形式并进行仿真实验验证,最后做出符合全部要求的实物。 关键词 逻辑信号;电平测试;高电平;低电平 毕业设计说明书(论文)中文摘要 毕业设计说明书(论文)外文摘要 Logic-level test signal design Abstract This paper, a logic level signal tester, it can be a convenient measurement that the level of potential through the availability of voice and sound frequencies to determine the level of the measured potential range. Thus can solve common circuit at some point in the logic level test its height electricity at ordinary times, it is not convenient by the multimeter or oscillograph instrument, etc .The design of the circuit mainly includes three parts: input circuit, the logic of the state of voice recognition and audio circuits have circuit. The main application of an integrated circuit operational amplifier nonlinear characteristics of a large open-loop gain, which can limit the production of dual comparators; used consisting of 555 timer Multivibrator circuit as a sound generated by the charging and discharging of the capacitor , a certain frequency signal. The logic input signal level is greater than or less than the high-low set potential, the audible sound circuit, if in between the high-low, the sound is not audible circuit. In this way the use of circuit design, component parameters of the calculation, select the appropriate cost of the device to determine the form and circuit simulation, and finally to meet all physical requirements. Keyword:slogic signal, level testing, high, low and circuit simulation, and finally to meet all physical requirements. Keywords logic signal, level testing, high, low 目录 1 绪论································································1 1.1课题研究及其意义····

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