存储器与可编程逻辑阵列-浙江大学.ppt

数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * 数字系统设计@浙大数芯 * In many instances, it is necessary to use various memory devices in the same memory system. The ROM portion is made up of two 8K x 8 devices (PROM-0 and PROM-1). The RAM section requires a single 8K x 8 device. The EEPROM available is only a 2K x 8 device. The memory system requires a decoder to select only one device at a time. This decoder divides the entire memory space (assuming 16 address bits) into 8K address blocks. The upper three address lines control the decoder. The 13 lower-order address lines are tied directly to the address inputs on the memory chips. The only exception to this the EEPROM, which has only 11 address lines for its 2-Kbyte capacity. The same contents of the EEPROM will also appear at the addresses 6800-6FFF, 7000-77FF, and 7800-7FFF. 数字系统设计@浙大数芯 * * ZDMC multiplexer demultiplexer 4x4 switch control control Multiplexer / Demultiplexer: Making Connections Direct point-to-point connections between gates Multiplexer: route one of many inputs to a single output Demultiplexer: route single input to one of many outputs * ZDMC two alternative forms for a 2:1 Mux truth table functional form logical form A Z0 I01 I1 I1 I0 A Z0 0 0 00 0 1 00 1 0 10 1 1 01 0 0 01 0 1 11 1 0 11 1 1 1 Z = A I0 + A I1 Multiplexers/Selectors Multiplexers/Selectors: general concept 2n data inputs, n control inputs (called selects), 1 output Used to connect 2n points to a single point Control signal pattern forms binary index of input connected to output * ZDMC 2:1 mux: Z = A I0 + A I1 4:1 mux: Z = A B I0 + A B I1 + A B I2 + A B I3 8:1 mux: Z = ABCI0 + ABCI1 + ABCI2 + ABCI3 +  ABCI4 + ABCI5 + ABCI6 + ABCI7 In general, Z = ? (mkIk)