- 1、本文档共8页,可阅读全部内容。
- 2、原创力文档(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。
- 3、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载。
- 4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
- 5、该文档为VIP文档,如果想要下载,成为VIP会员后,下载免费。
- 6、成为VIP后,下载本文档将扣除1次下载权益。下载后,不支持退款、换文档。如有疑问请联系我们。
- 7、成为VIP后,您将拥有八大权益,权益包括:VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
- 8、VIP文档为合作方或网友上传,每下载1次, 网站将根据用户上传文档的质量评分、类型等,对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档
查看更多
Exploring DRAM Cache Architectures for CMP Server Platforms
Li Zhao, Ravi Iyer, Ramesh Illikkal and Don Newell
System Technology Lab, Intel Corporation, Hillsboro, OR
Email: li.zhao, ravishankar.iyer, ramesh.g.illikkal, donald.newell @
Abstract other potential solution is to add an off-chip DRAM cache
in between the last-level processor cache and the DRAM
As dual-core and quad-core processors arrive in the memory. Using DRAM allows for a much larger capacity
marketplace, the momentum behind CMP architectures but at a somewhat longer latency. Previous studies [10][21]
continues to grow strong. As more and more cores/threads and our own internal analysis has shown that DRAM-based
are placed on-die, the pressure on the memory subsystem is caches (using Multi-Chip Package or 3D-stacking technol-
rapidly increasing. To address this issue, we explore DRAM ogy) can be designed to provide twice the bandwidth of
cache architectures for CMP platforms. In this paper, we main memory at about one third of the memory latency. Our
investigate the impact of introducing a low latency, large goal is to take advantage of this potential for CMP-based
capacity and high bandwidth DRAM-based cache between server platforms. To our knowledge, this is the first study
the last level SRAM cache and memory subsystem. We first that explores the potential of DRAM cache and evaluates
show the potential benefits of large DRAM caches for key the architectural options for CMP-based server platforms in
commercial server workloads. As the primary hurdle to detail.
achieving these benefits with DRAM
您可能关注的文档
- the locality-aware adaptive cache coherence protocol高级体系结构.pdf
- die-stacked dram caches for servers高级体系结构.pdf
- die stacking microarchitecture高级体系结构.pdf
- bit mapping for balanced pcm cell programming高级体系结构.pdf
- adaptive filter-based DRAM caching for CMP Server Platforms高级体系结构.pdf
- a new perspective for efficient virtual-cache coherence高级体系结构.pdf
- architecture-level modeling for 3d die-stacked dram main memory高级体系结构.pdf
- 3d-stacked memory architecture for muti-core processors高级体系结构.pdf
- 03_caches高级体系结构.pdf
- 1 DRAM架构高级体系结构.docx
文档评论(0)