bit mapping for balanced pcm cell programming高级体系结构.pdfVIP

Bit Mapping for Balanced PCM Cell Programming Yu Du, Miao Zhou, Bruce R. Childers, Daniel Mossé and Rami Melhem Department of Computer Science University of Pittsburgh Pittsburgh, PA, 15260 {fisherdu,miaozhou,childers,mosse,melhem}@cs.pitt.edu ABSTRACT can be stored without refresh operations, allowing PCM Write bandwidth is an inherent performance bottleneck for chips to be powered off when not in use, to save energy. Phase Change Memory (PCM) for two reasons. First, PCM Second, unlike NAND flash memory, PCM is bit-addressable cells have long programming time, and second, only a limited and has a read access latency comparable to DRAM. Third, number of PCM cells can be programmed concurrently due PCM is scalable: an 8Gb PCM chip has been demonstrated to programming current and write circuit constraints, in 20nm process technology [3]. Despite promise, PCM has For each PCM write, the data bits of the write request weaknesses, which are the subject of much research. Wear- are typically mapped to multiple cell groups and processed leveling techniques have been proposed to evenly distribute in parallel. We observed that an unbalanced distribution of writes to PCM memory lines [35, 21, 23]. Fault-tolerance modified data bits among cell groups significantly increases techniques have been proposed to protect PCM chips from PCM write time and hurts effective write bandwidth. To ad- weak cell failures [22, 19, 31, 8, 9].1 Write-pausing has bee